Invention Grant
- Patent Title: Method to control delay between lanes
- Patent Title (中): 控制车道延误的方法
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Application No.: US11322059Application Date: 2005-12-28
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Publication No.: US08166215B2Publication Date: 2012-04-24
- Inventor: Srikrishnan Venkataraman , Jayashree Kar , Sudarshan D. Solanki , Priyavadan Ramdas Patel , Michael M. DeSmith , David G. Figueroa
- Applicant: Srikrishnan Venkataraman , Jayashree Kar , Sudarshan D. Solanki , Priyavadan Ramdas Patel , Michael M. DeSmith , David G. Figueroa
- Applicant Address: US CA Santa Clara
- Assignee: Intel Corporation
- Current Assignee: Intel Corporation
- Current Assignee Address: US CA Santa Clara
- Agency: Caven & Aghevli LLC
- Main IPC: G06F3/00
- IPC: G06F3/00 ; G06F5/00 ; H03K3/00 ; H03K17/16 ; G03F1/00

Abstract:
Method and apparatus to control delay between lanes in an I/O interface is disclosed. To control the delay between the lanes in the I/O system a programmed delay may be determined and introduced between the lanes. For this purpose the effective time “T” of the lanes is determined. The number of lanes “N” in the I/O interface is identified. The programmed lane to lane delay “D” is determined and a delay circuit having the programmed delay may be introduced between the lanes to reduce AC peak to peak noise in the I/O system.
Public/Granted literature
- US20070150197A1 Method to control delay between lanes Public/Granted day:2007-06-28
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