A programmable logic device includes a hard-logic portion that selectively aggregates bandwidth of data ports and maps logically and physically the transactions from these ports. The memory interface structure is a part of a hard-logic portion that includes random access memories (RAMs), multiplexers, and pointers that allow static or dynamic bandwidth configuration as function of instruments examining the system traffic using queues. The interface allows many initiators having many logical threads to share and use many physical threads in different queue modules.