Invention Grant
US08166357B2 Implementing logic security feature for disabling integrated circuit test ports ability to scanout data
有权
实现逻辑安全功能，禁用集成电路测试端口扫描数据的能力
- Patent Title: Implementing logic security feature for disabling integrated circuit test ports ability to scanout data
- Patent Title (中): 实现逻辑安全功能，禁用集成电路测试端口扫描数据的能力
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Application No.: US11964093Application Date: 2007-12-26
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Publication No.: US08166357B2Publication Date: 2012-04-24
- Inventor: David Warren Pruden , Dennis Martin Rickert , Brian Andrew Schuelke
- Applicant: David Warren Pruden , Dennis Martin Rickert , Brian Andrew Schuelke
- Applicant Address: US NY Armonk
- Assignee: International Business Machines Corporation
- Current Assignee: International Business Machines Corporation
- Current Assignee Address: US NY Armonk
- Agent Joan Pennington
- Main IPC: G01R31/28
- IPC: G01R31/28
Abstract:
A method and apparatus for implementing integrated circuit security features are provided to selectively disable testability features on an integrated circuit chip. A test disable logic circuit receives a test enable signal and responsive to the test enable signal set for a test mode, establishes a test mode and disables ASIC signals. Responsive to the test enable signal not being set, the ASIC signals are enabled for a functional mode and the testability features on the integrated circuit chip are disabled. When the functional mode is enabled, the test disable logic circuit prevents the test mode from being established while the integrated circuit chip is powered up.
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