Invention Grant
- Patent Title: Method of shield line placement for semiconductor integrated circuit, design apparatus for semiconductor integrated circuit, and design program for semiconductor integrated circuit
- Patent Title (中): 半导体集成电路屏蔽线放置方法,半导体集成电路设计装置及半导体集成电路设计程序
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Application No.: US12216377Application Date: 2008-07-02
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Publication No.: US08166443B2Publication Date: 2012-04-24
- Inventor: Katsushi Aoki , Takahiro Toda , Junya Yamasaki , Shinichi Iida , Hiroki Murakami
- Applicant: Katsushi Aoki , Takahiro Toda , Junya Yamasaki , Shinichi Iida , Hiroki Murakami
- Applicant Address: JP Kawasaki
- Assignee: Fujitsu Limited
- Current Assignee: Fujitsu Limited
- Current Assignee Address: JP Kawasaki
- Agency: Staas & Halsey LLP
- Main IPC: G06F17/50
- IPC: G06F17/50

Abstract:
A semiconductor integrated circuit design apparatus includes: an association information creating unit which creates association information for associating wiring information of a signal line with wiring information of a shield line placed for the signal line; an association information storage unit which stores the thus created association information; and a shield wiring unit which, when the placement of the signal line is changed, changes in interlinking fashion with the changed placement the placement of the shield line that is associated with the signal line by the association information.
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