High performance stress-enhanced MOSFETS using Si:C and SiGe epitaxial source/drain and method of manufacture

Invention Grant

US08168489B2 High performance stress-enhanced MOSFETS using Si:C and SiGe epitaxial source/drain and method of manufacture 有权

Title translation: 使用Si：C和SiGe外延源/漏极的高性能应力增强MOSFETs及其制造方法

Please log in to see more content

Patent Title: High performance stress-enhanced MOSFETS using Si:C and SiGe epitaxial source/drain and method of manufacture
Patent Title (中): 使用Si：C和SiGe外延源/漏极的高性能应力增强MOSFETs及其制造方法
Application No.: US11782429

Application Date: 2007-07-24
Publication No.: US08168489B2

Publication Date: 2012-05-01
Inventor: Huajie Chen , Dureseti Chidambarrao , Omer H. Dokumaci
Applicant: Huajie Chen , Dureseti Chidambarrao , Omer H. Dokumaci
Applicant Address: US NY Armonk
Assignee: International Business Machines Corporation
Current Assignee: International Business Machines Corporation
Current Assignee Address: US NY Armonk
Agency: Roberts Mlotkowski Safran & Cole, P.C.
Agent Joseph P. Abate
Main IPC: H01L21/8238
IPC: H01L21/8238 ; H01L21/336

High performance stress-enhanced MOSFETS using Si:C and SiGe epitaxial source/drain and method of manufacture

Abstract:

A semiconductor device and method of manufacturing a semiconductor device. The semiconductor device includes channels for a pFET and an nFET. A SiGe layer is selectively grown in the source and drain regions of the pFET channel and a Si:C layer is selectively grown in source and drain regions of the nFET channel. The SiGe and Si:C layer match a lattice network of the underlying Si layer to create a stress component. In one implementation, this causes a compressive component in the pFET channel and a tensile component in the nFET channel.

Abstract(Chinese):

半导体器件及半导体器件的制造方法。半导体器件包括用于pFET和nFET的沟道。在pFET沟道的源极和漏极区域选择性地生长SiGe层，并且在nFET沟道的源极和漏极区域选择性地生长Si：C层。 SiGe和Si：C层与下层Si层的晶格网络匹配以产生应力分量。在一个实现中，这导致pFET沟道中的压缩分量和nFET沟道中的拉伸分量。

Public/Granted literature

US20070264783A1 HIGH PERFORMANCE STRESS-ENHANCED MOSFETS USING SI:C AND SIGE EPITAXIAL SOURCE/DRAIN AND METHOD OF MANUFACTURE Public/Granted day:2007-11-15

Information query

Espacenet

IPC分类:

H	电学
H01	基本电气元件
H01L	半导体器件；其他类目中不包括的电固体器件（使用半导体器件的测量入G01；一般电阻器入H01C；磁体、电感器、变压器入H01F；一般电容器入H01G；电解型器件入H01G9/00；电池组、蓄电池入H01M；波导管、谐振器或波导型线路入H01P；线路连接器、汇流器入H01R；受激发射器件入H01S；机电谐振器入H03H；扬声器、送话器、留声机拾音器或类似的声机电传感器入H04R；一般电光源入H05B；印刷电路、混合电路、电设备的外壳或结构零部件、电气元件的组件的制造入H05K；在具有特殊应用的电路中使用的半导体器件见应用相关的小类）
H01L21/00	专门适用于制造或处理半导体或固体器件或其部件的方法或设备
H01L21/70	.由在一共用基片内或其上形成的多个固态组件或集成电路组成的器件或其部件的制造或处理；集成电路器件或其特殊部件的制造（由预制电组件组成的组装件的制造入H05K3/00，H05K13/00）
H01L21/77	..在公共衬底中或上面形成的由许多固态元件或集成电路组成的器件的制造或处理（电可编程只读存储器或其多步骤的制造方法入H01L27/115）
H01L21/78	...把衬底连续地分成多个独立的器件（改变表面物理特性或者半导体形状的切割入H01L21/304）
H01L21/82	....制造器件，例如每一个由许多元件组成的集成电路
H01L21/822	.....衬底是采用硅工艺的半导体的（H01L21/8258优先）
H01L21/8232	......场效应工艺
H01L21/8234	.......MIS工艺
H01L21/8238	........互补场效应晶体管，例如CMOS