Invention Grant
- Patent Title: Method of fabricating transistor with epitaxial layers having different germanium concentrations
- Patent Title (中): 制造具有不同锗浓度的外延层的晶体管的方法
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Application No.: US13107789Application Date: 2011-05-13
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Publication No.: US08168505B2Publication Date: 2012-05-01
- Inventor: Cheol Hoon Yang , Yong Han Jeon
- Applicant: Cheol Hoon Yang , Yong Han Jeon
- Applicant Address: KR Gwangju-si, Gyeonggi-do
- Assignee: Jusung Engineering Co., Ltd.
- Current Assignee: Jusung Engineering Co., Ltd.
- Current Assignee Address: KR Gwangju-si, Gyeonggi-do
- Agency: Portland IP Law LLC
- Priority: KR10-2007-0109926 20071031
- Main IPC: H01L21/331
- IPC: H01L21/331 ; H01L27/148
Abstract:
A method of fabricating a transistor is provided. The transistor includes a SiGe epitaxial layer formed in a recess region of a substrate at both side of a gate electrode and a SiGe capping layer formed on the SiGe epitaxial layer. The transistor further includes a SiGe seed layer formed under the SiGe epitaxial layer and a silicon capping layer formed on the SiGe capping layer.
Public/Granted literature
- US20110212604A1 METHOD OF FABRICATING TRANSISTOR Public/Granted day:2011-09-01
Information query
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