Invention Grant
- Patent Title: Non-volatile memory with erase gate on isolation zones
- Patent Title (中): 带隔离区擦除门的非易失性存储器
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Application No.: US12726087Application Date: 2010-03-17
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Publication No.: US08168524B2Publication Date: 2012-05-01
- Inventor: Robertus T. F. van Schaijk , Michiel J. van Duuren
- Applicant: Robertus T. F. van Schaijk , Michiel J. van Duuren
- Applicant Address: NL Eindhoven
- Assignee: NXP B.V.
- Current Assignee: NXP B.V.
- Current Assignee Address: NL Eindhoven
- Priority: EP04102703 20040615
- Main IPC: H01L21/3205
- IPC: H01L21/3205 ; H01L21/4763

Abstract:
The present invention provides a non-volatile memory device and a method for manufacturing such a device. The device comprises a floating gate (16), a control gate (19) and a separate erase gate (10). The erase gate (10) is provided in or on isolation zones (2) provided in the substrate (1). Because of that, the erase gates (10) do not add to the cell size. The capacitance between the erase gate (10) and the floating gate (16) is small compared with the capacitance between the control gate (19) and the floating gate (16), and the charged floating gate (16) is erased by Fowler-Nordheim tunneling through the oxide layer between the erase gate (10) and the floating gate (16).
Public/Granted literature
- US20100173488A1 NON-VOLATILE MEMORY WITH ERASE GATE ON ISOLATION ZONES Public/Granted day:2010-07-08
Information query
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