Invention Grant
- Patent Title: Gate stacks and semiconductor constructions
- Patent Title (中): 门叠和半导体结构
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Application No.: US12938114Application Date: 2010-11-02
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Publication No.: US08169032B2Publication Date: 2012-05-01
- Inventor: D. V. Nirmal Ramaswamy , Venkatesan Ananthan
- Applicant: D. V. Nirmal Ramaswamy , Venkatesan Ananthan
- Applicant Address: US ID Boise
- Assignee: Micron Technology, Inc.
- Current Assignee: Micron Technology, Inc.
- Current Assignee Address: US ID Boise
- Agency: Wells St. John P.S.
- Main IPC: H01L29/78
- IPC: H01L29/78 ; H01L27/092
Abstract:
The invention includes methods of forming PMOS transistors and NMOS transistors. The NMOS transistors can be formed to have a thin silicon-containing material between a pair of metal nitride materials, while the PMOS transistors are formed to have the metal nitride materials directly against one another. The invention also includes constructions which contain an NMOS transistor gate stack having a thin silicon-containing material between a pair of metal nitride materials. The silicon-containing material can, for example, consist of silicon, conductively-doped silicon, or silicon oxide; and can have a thickness of less than or equal to about 30 angstroms.
Public/Granted literature
- US20110042754A1 Gate Stacks and Semiconductor Constructions Public/Granted day:2011-02-24
Information query
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