Invention Grant
US08169037B2 Semiconductor integrated circuit including transistor having diffusion layer formed at outside of element isolation region for preventing soft error
失效
包括晶体管的半导体集成电路，其具有形成在元件隔离区域外部的扩散层，以防止软错误
- Patent Title: Semiconductor integrated circuit including transistor having diffusion layer formed at outside of element isolation region for preventing soft error
- Patent Title (中): 包括晶体管的半导体集成电路，其具有形成在元件隔离区域外部的扩散层，以防止软错误
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Application No.: US12453178Application Date: 2009-04-30
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Publication No.: US08169037B2Publication Date: 2012-05-01
- Inventor: Hiroshi Furuta , Shouzou Uchida , Muneaki Matsushige , Junji Monden
- Applicant: Hiroshi Furuta , Shouzou Uchida , Muneaki Matsushige , Junji Monden
- Applicant Address: JP Kawasaki-shi, Kanagawa
- Assignee: Renesas Electronics Corporation
- Current Assignee: Renesas Electronics Corporation
- Current Assignee Address: JP Kawasaki-shi, Kanagawa
- Agency: McGinn IP Law Group, PLLC
- Priority: JP2008-134095 20080522; JP2009-096373 20090410
- Main IPC: H01L29/76
- IPC: H01L29/76 ; H01L29/94 ; H01L31/062 ; H01L31/113 ; H01L31/119
Abstract:
A MISFET includes a drain diffusion layer of a first conductivity type, a source diffusion layer of the first conductivity type, a gate electrode, and a substrate/well of a second conductivity type. In the MISFET, first diffusion layers of the first conductivity type are provided at two or more positions at predetermined intervals with an isolation therebetween respectively. The two or more positions are facing at least two sides of the element isolation insulation around the drain diffusion layer. A second diffusion layer of the second conductivity type is provided so as to be close to or to come in contact with the source diffusion layer.
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