Invention Grant
US08169058B2 Semiconductor device and method of stacking die on leadframe electrically connected by conductive pillars
有权
半导体器件和在导电框架上通过导电柱电连接的芯片堆叠的方法
- Patent Title: Semiconductor device and method of stacking die on leadframe electrically connected by conductive pillars
- Patent Title (中): 半导体器件和在导电框架上通过导电柱电连接的芯片堆叠的方法
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Application No.: US12545357Application Date: 2009-08-21
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Publication No.: US08169058B2Publication Date: 2012-05-01
- Inventor: Reza A. Pagaila , Byung Tai Do , Linda Pei Ee Chua
- Applicant: Reza A. Pagaila , Byung Tai Do , Linda Pei Ee Chua
- Applicant Address: SG Singapore
- Assignee: STATS ChipPAC, Ltd.
- Current Assignee: STATS ChipPAC, Ltd.
- Current Assignee Address: SG Singapore
- Agency: Patent Law Group: Atkins & Associates, P.C.
- Agent Robert D. Atkins
- Main IPC: H01L23/58
- IPC: H01L23/58

Abstract:
A semiconductor device has a first semiconductor die mounted to a first contact pad on a leadframe or substrate with bumps. A conductive pillar is formed over a second semiconductor die. The second die is mounted over the first die by electrically connecting the conductive pillar to a second contact pad on the substrate with bumps. The second die is larger than the first die. An encapsulant is deposited over the first and second die. Alternatively, the conductive pillars are formed over the substrate around the first die. A heat sink is formed over the second die, and a thermal interface material is formed between the first and second die. An underfill material is deposited under the first semiconductor die. A shielding layer is formed between the first and second die. An interconnect structure can be formed over the second contact pad of the substrate.
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