Invention Grant
- Patent Title: Interconnect structures having lead-free solder bumps
- Patent Title (中): 具有无铅焊料凸块的互连结构
-
Application No.: US12537001Application Date: 2009-08-06
-
Publication No.: US08169076B2Publication Date: 2012-05-01
- Inventor: Mirng-Ji Lii , Chien-Hsiun Lee , Chen-Hua Yu , Shin-Puu Jeng , Chin-Yu Ku
- Applicant: Mirng-Ji Lii , Chien-Hsiun Lee , Chen-Hua Yu , Shin-Puu Jeng , Chin-Yu Ku
- Applicant Address: TW Hsin-Chu
- Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
- Current Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
- Current Assignee Address: TW Hsin-Chu
- Agency: Slater & Matsil, L.L.P.
- Main IPC: H01L23/498
- IPC: H01L23/498

Abstract:
An integrated circuit structure includes a semiconductor substrate, and a polyimide layer over the semiconductor substrate. An under-bump-metallurgy (UBM) has a first portion over the polyimide layer, and a second portion level with the polyimide layer. A first solder bump and a second solder bump are formed over the polyimide layer, with a pitch between the first solder bump and the second solder bump being no more than 150 μm. A width of the UBM equals one-half of the pitch plus a value greater than 5 μm.
Public/Granted literature
- US20100314756A1 Interconnect Structures Having Lead-Free Solder Bumps Public/Granted day:2010-12-16
Information query
IPC分类: