In a parallel-serial converter circuit of a multistage configuration, there is formed a clock propagation path so that when multistage connected data converters are operated according to the timing of a clock signal, a reference clock signal or a clock signal in which the reference clock signal has been frequency-converted, is given sequentially to the data converter of the first stage up to the data converter of the final stage. As a result, even in a case where variations occur in power supply voltage, timing deviation of data signals and clock signals input to the data converters of the second and subsequent stages can be suppressed, and parallel-serial conversion of high-speed data signals can be reliably executed.