A thin film transistor array panel includes; a substrate including a display area and a peripheral area, a display area signal line disposed in the display area, a display area thin film transistor connected to the display area signal line, a plurality of peripheral area signal lines disposed in the peripheral area, a light-blocking member disposed on the display area signal line, the display area thin film transistor, and the plurality of peripheral area signal lines, a transparent connection electrically connecting the plurality of peripheral area signal lines to each other through a plurality of first contact holes, and a pixel electrode connected to the display area thin film transistor through a second contact hole, wherein an area density of the first contact hole in the peripheral area is less than or equal to about three times an area density of the second contact hole in the display area.