Invention Grant
- Patent Title: Internal memory for transistor outline packages
- Patent Title (中): 用于晶体管外形封装的内部存储器
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Application No.: US12133101Application Date: 2008-06-04
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Publication No.: US08170077B2Publication Date: 2012-05-01
- Inventor: Radek Sedlacik
- Applicant: Radek Sedlacik
- Applicant Address: US CA Sunnyvale
- Assignee: Finisar Corporation
- Current Assignee: Finisar Corporation
- Current Assignee Address: US CA Sunnyvale
- Agency: Morgan, Lewis & Bockius LLP
- Main IPC: G01R31/26
- IPC: G01R31/26 ; H01S5/026

Abstract:
A transistor outline (TO) package includes a housing having a window and a substrate. Circuitry is coupled to the substrate within the housing. The circuitry comprises a laser diode and memory configured to store information related to the TO package. Electrical connectors are coupled to the substrate at the opposite side to the circuitry. At least one of the electrical connectors is electrically connected to the memory. A disclosed method includes assembling a TO package, testing the TO package, storing results of the testing in memory, and making the information stored in the memory, including the results of the testing, available to a device external to the TO package. The TO package includes a laser diode and memory configured to store information related to the TO package.
Public/Granted literature
- US20090302881A1 Internal Memory for Transistor Outline Packages Public/Granted day:2009-12-10
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