Invention Grant
- Patent Title: Clock data recovery circuit
- Patent Title (中): 时钟数据恢复电路
-
Application No.: US12654204Application Date: 2009-12-14
-
Publication No.: US08170168B2Publication Date: 2012-05-01
- Inventor: Yoshinobu Oshima
- Applicant: Yoshinobu Oshima
- Applicant Address: JP Kawasaki-shi, Kanagawa
- Assignee: Renesas Electronics Corporation
- Current Assignee: Renesas Electronics Corporation
- Current Assignee Address: JP Kawasaki-shi, Kanagawa
- Agency: McGinn IP Law Group, PLLC
- Priority: JP2008-319702 20081216
- Main IPC: H04L7/02
- IPC: H04L7/02
Abstract:
A simple circuit that supports high and low data rates is provided. The circuit includes: a detection circuit 11 for detecting whether D1≠D2 or D1≠D3, assuming that logical values of an input data signal DATAIN sampled at timings t1, t2, and t3 (t2
Public/Granted literature
- US20100148832A1 Clock data recovery circuit Public/Granted day:2010-06-17
Information query
