Invention Grant
US08171261B2 Method and system for accessing memory in parallel computing using load fencing instructions
有权
使用负载击剑指令并行计算访问存储器的方法和系统
- Patent Title: Method and system for accessing memory in parallel computing using load fencing instructions
- Patent Title (中): 使用负载击剑指令并行计算访问存储器的方法和系统
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Application No.: US10654573Application Date: 2003-09-02
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Publication No.: US08171261B2Publication Date: 2012-05-01
- Inventor: Salvador Palanca , Stephen A. Fischer , Subramaniam Maiyuran , Shekoufeh Qawami
- Applicant: Salvador Palanca , Stephen A. Fischer , Subramaniam Maiyuran , Shekoufeh Qawami
- Applicant Address: US CA Santa Clara
- Assignee: Intel Corporation
- Current Assignee: Intel Corporation
- Current Assignee Address: US CA Santa Clara
- Agency: Blakely, Sokoloff, Taylor & Zafman LLP
- Main IPC: G06F15/00
- IPC: G06F15/00 ; G06F9/30 ; G06F9/40
Abstract:
A system and method for fencing memory accesses. Memory loads can be fenced, or all memory access can be fenced. The system receives a fencing instruction that separates memory access instructions into older accesses and newer accesses. A buffer within the memory ordering unit is allocated to the instruction. The access instructions newer than the fencing instruction are stalled. The older access instructions are gradually retired. When all older memory accesses are retired, the fencing instruction is dispatched from the buffer.
Public/Granted literature
- US20040044883A1 MFENCE and LFENCE micro-architectural implementation method and system Public/Granted day:2004-03-04
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