Invention Grant
US08171326B2 L1 flush mechanism to flush cache for power down and handle coherence during flush and/or after power down
有权
L1冲洗机构刷新缓存以断电并处理冲水和/或断电后的一致性
- Patent Title: L1 flush mechanism to flush cache for power down and handle coherence during flush and/or after power down
- Patent Title (中): L1冲洗机构刷新缓存以断电并处理冲水和/或断电后的一致性
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Application No.: US12785842Application Date: 2010-05-24
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Publication No.: US08171326B2Publication Date: 2012-05-01
- Inventor: James B. Keller , Tse-Yu Yeh , Ramesh Gunna , Brian J. Campbell
- Applicant: James B. Keller , Tse-Yu Yeh , Ramesh Gunna , Brian J. Campbell
- Applicant Address: US CA Cupertino
- Assignee: Apple Inc.
- Current Assignee: Apple Inc.
- Current Assignee Address: US CA Cupertino
- Agency: Meyertons, Hood, Kivlin, Kowert & Goetzel, P.C.
- Agent Lawrence J. Merkel
- Main IPC: G06F1/32
- IPC: G06F1/32
Abstract:
In one embodiment, a processor comprises a data cache configured to store a plurality of cache blocks and a control unit coupled to the data cache. The control unit is configured to flush the plurality of cache blocks from the data cache responsive to an indication that the processor is to transition to a low power state in which one or more clocks for the processor are inhibited.
Public/Granted literature
- US20100235670A1 Fast L1 Flush Mechanism Public/Granted day:2010-09-16
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