Invention Grant
US08171335B2 Clock timing calibration circuit and clock timing calibration method for calibrating phase difference between different clock signals and related analog-to-digital conversion system using the same
有权
时钟定时校准电路和时钟定时校准方法，用于校准不同时钟信号之间的相位差和使用相同模数转换系统的相关模数转换系统
- Patent Title: Clock timing calibration circuit and clock timing calibration method for calibrating phase difference between different clock signals and related analog-to-digital conversion system using the same
- Patent Title (中): 时钟定时校准电路和时钟定时校准方法，用于校准不同时钟信号之间的相位差和使用相同模数转换系统的相关模数转换系统
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Application No.: US12479877Application Date: 2009-06-08
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Publication No.: US08171335B2Publication Date: 2012-05-01
- Inventor: Jen-Che Tsai
- Applicant: Jen-Che Tsai
- Applicant Address: TW Science-Based Industrial Park, Hsin-Chu
- Assignee: Mediatek Inc.
- Current Assignee: Mediatek Inc.
- Current Assignee Address: TW Science-Based Industrial Park, Hsin-Chu
- Agent Winston Hsu; Scott Margo
- Main IPC: G06F1/04
- IPC: G06F1/04
Abstract:
A clock timing calibration circuit includes a clock timing adjusting unit and a calibration control unit. The clock timing adjusting unit is for receiving an incoming reference clock signal and selectively adjusting the received reference clock signal to generate a first clock signal according to a calibration control signal. The incoming reference clock has a predetermined phase and a predetermined frequency, The calibration control unit is for checking if the phase difference between the first clock signal and a second clock signal satisfies a predetermined criterion, and for adjusting the calibration control signal when the phase difference between the first clock signal and the second clock signal does not satisfy the predetermined criterion. The predetermined criterion is to check if the phase difference falls within a specific range associated with a clock period of one of the first clock signal and the second clock signal.
Public/Granted literature
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