Sequential storage circuitry for a integrated circuit is provided, comprising a first storage element, a second storage element and an additional storage element. The first storage element stores, during a first phase of a clock signal, a first indication of an input data value received by the sequential storage circuitry. The second storage element is coupled to an output of the first storage element, and stores a second indication of the input data value during a second phase of the clock signal. The additional storage element is driven by a pulse signal derived from the clock signal, and is arranged on occurrence of that pulse signal to store a third indication of the input data value. Error detection circuitry is then provided for detecting a single event upset error in either the first storage element or the second storage element. In particular, during the first phase of the clock signal, the error detection circuitry detects the single event upset error in the first storage element if there is a difference in the input data value as indicated by the first indication and the third indication. Further, during the second phase of the clock signal, the error detection circuitry detects a single event upset error in the second storage element if there is a difference in the input data value as indicated by the second indication and the third indication. Such an arrangement provides a simple mechanism for detecting soft errors in both the first storage element and the second storage element using only one additional storage element.