Invention Grant
US08171433B2 Method of calculating pattern-failure-occurrence-region, computer program product, pattern-layout evaluating method, and semiconductor-device manufacturing method
有权
计算图案故障发生区域，计算机程序产品，图案布局评估方法和半导体器件制造方法的方法
- Patent Title: Method of calculating pattern-failure-occurrence-region, computer program product, pattern-layout evaluating method, and semiconductor-device manufacturing method
- Patent Title (中): 计算图案故障发生区域，计算机程序产品，图案布局评估方法和半导体器件制造方法的方法
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Application No.: US12554495Application Date: 2009-09-04
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Publication No.: US08171433B2Publication Date: 2012-05-01
- Inventor: Masanori Takahashi , Toshiya Kotani , Satoshi Tanaka
- Applicant: Masanori Takahashi , Toshiya Kotani , Satoshi Tanaka
- Applicant Address: JP Tokyo
- Assignee: Kabushiki Kaisha Toshiba
- Current Assignee: Kabushiki Kaisha Toshiba
- Current Assignee Address: JP Tokyo
- Agency: Finnegan, Henderson, Farabow, Garrett & Dunner, L.L.P.
- Priority: JP2008-248785 20080926
- Main IPC: G06F17/50
- IPC: G06F17/50
Abstract:
Method of calculating pattern-failure-occurrence-region comprising calculating a pattern failure occurrence region using relation information and a layout used for forming a convex section, the relation information being a relation between a distance from a formed pattern in a film to cover the convex section on a substrate to the convex section and a region in the film in which a shape of the formed pattern cannot satisfy a predetermined condition because of influence of the convex section.
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