Invention Grant
US08173499B2 Method of fabricating a gate stack integration of complementary MOS device
有权
制造互补MOS器件栅极堆叠集成的方法
- Patent Title: Method of fabricating a gate stack integration of complementary MOS device
- Patent Title (中): 制造互补MOS器件栅极堆叠集成的方法
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Application No.: US12750413Application Date: 2010-03-30
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Publication No.: US08173499B2Publication Date: 2012-05-08
- Inventor: Shu-Wei Chung , Kuo-Feng Yu , Shyue-Shyh Lin
- Applicant: Shu-Wei Chung , Kuo-Feng Yu , Shyue-Shyh Lin
- Applicant Address: TW Hsin-Chu
- Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
- Current Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
- Current Assignee Address: TW Hsin-Chu
- Agency: Slater & Matsil, L.L.P.
- Main IPC: H01L21/8238
- IPC: H01L21/8238 ; H01L29/788
Abstract:
A method of forming an integrated circuit structure includes providing a substrate comprising a first device region and a second device region; forming an oxide cap over the substrate and in the first device region and the second device region; forming a first metal layer over the oxide cap, wherein the first metal layer has a first portion in the first device region and a second portion in the second device region; forming a mask to cover the second portion of the first metal layer, wherein the first portion of the first metal layer is exposed; removing the first portion of the first metal layer and the oxide cap from the first device region; removing the mask; and forming a second metal layer in the first device region and the second device region, wherein the second metal layer in the second device region is over the second portion of the first metal layer.
Public/Granted literature
- US20100317181A1 Gate Stack Integration of Complementary MOS Devices Public/Granted day:2010-12-16
Information query
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