Invention Grant
US08173501B2 Reduced STI topography in high-K metal gate transistors by using a mask after channel semiconductor alloy deposition
有权
通过在沟道半导体合金沉积后使用掩模,在高K金属栅极晶体管中降低了STI形貌
- Patent Title: Reduced STI topography in high-K metal gate transistors by using a mask after channel semiconductor alloy deposition
- Patent Title (中): 通过在沟道半导体合金沉积后使用掩模,在高K金属栅极晶体管中降低了STI形貌
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Application No.: US12964136Application Date: 2010-12-09
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Publication No.: US08173501B2Publication Date: 2012-05-08
- Inventor: Stephan Kronholz , Markus Lenski , Richard Carter
- Applicant: Stephan Kronholz , Markus Lenski , Richard Carter
- Applicant Address: KY Grand Cayman
- Assignee: Globalfoundries Inc.
- Current Assignee: Globalfoundries Inc.
- Current Assignee Address: KY Grand Cayman
- Agency: Williams, Morgan & Amerson, P.C.
- Priority: DE102010028459 20100430
- Main IPC: H01L21/8238
- IPC: H01L21/8238

Abstract:
In a manufacturing strategy for providing high-k metal gate electrode structures in an early manufacturing stage, process-related non-uniformities during and after the patterning of the gate electrode structures may be reduced by providing a superior surface topography. To this end, the material loss in the isolation region may generally be reduced and a more symmetrical exposure to reactive etch atmospheres during the subsequent removal of the growth mask may be accomplished by providing an additional etch mask when removing the growth mask from the active regions of N-channel transistors, after the growth of the threshold adjusting semiconductor material on the active regions of the P-channel transistors.
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