Fabrication of source/drain extensions with ultra-shallow junctions

Invention Grant

US08173503B2 Fabrication of source/drain extensions with ultra-shallow junctions 有权

Title translation: 源极/漏极扩展与超浅结的制造

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Patent Title: Fabrication of source/drain extensions with ultra-shallow junctions
Patent Title (中): 源极/漏极扩展与超浅结的制造
Application No.: US12617955

Application Date: 2009-11-13
Publication No.: US08173503B2

Publication Date: 2012-05-08
Inventor: Yihang Chiu , Chu-Yun Fu
Applicant: Yihang Chiu , Chu-Yun Fu
Applicant Address: TW Hsin-Chu
Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
Current Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
Current Assignee Address: TW Hsin-Chu
Agency: Slater & Matsil, L.L.P.
Main IPC: H01L21/8238
IPC: H01L21/8238 ; H01L21/336

Fabrication of source/drain extensions with ultra-shallow junctions

Abstract:

A method of forming an integrated circuit device includes providing a semiconductor substrate; forming a gate structure on the semiconductor substrate; and performing a pre-amorphized implantation (PAI) by implanting a first element selected from a group consisting essentially of indium and antimony to a top portion of the semiconductor substrate adjacent to the gate structure. The method further includes, after the step of performing the PAI, implanting a second element different from the first element into the top portion of the semiconductor substrate. The second element includes a p-type element when the first element includes indium, and includes an n-type element when the first element includes antimony.

Abstract(Chinese):

形成集成电路器件的方法包括提供半导体衬底; 在所述半导体衬底上形成栅极结构; 以及通过将选自由铟和锑组成的组中的第一元素注入到与栅极结构相邻的半导体衬底的顶部部分来执行预非晶化注入（PAI）。该方法还包括在执行PAI的步骤之后，将不同于第一元件的第二元件注入到半导体衬底的顶部。当第一元素包括铟时，第二元素包括p型元素，并且当第一元素包括锑时包括n型元素。

Public/Granted literature

US20100216288A1 Fabrication of Source/Drain Extensions with Ultra-Shallow Junctions Public/Granted day:2010-08-26

Information query

Espacenet

IPC分类:

H	电学
H01	基本电气元件
H01L	半导体器件；其他类目中不包括的电固体器件（使用半导体器件的测量入G01；一般电阻器入H01C；磁体、电感器、变压器入H01F；一般电容器入H01G；电解型器件入H01G9/00；电池组、蓄电池入H01M；波导管、谐振器或波导型线路入H01P；线路连接器、汇流器入H01R；受激发射器件入H01S；机电谐振器入H03H；扬声器、送话器、留声机拾音器或类似的声机电传感器入H04R；一般电光源入H05B；印刷电路、混合电路、电设备的外壳或结构零部件、电气元件的组件的制造入H05K；在具有特殊应用的电路中使用的半导体器件见应用相关的小类）
H01L21/00	专门适用于制造或处理半导体或固体器件或其部件的方法或设备
H01L21/70	.由在一共用基片内或其上形成的多个固态组件或集成电路组成的器件或其部件的制造或处理；集成电路器件或其特殊部件的制造（由预制电组件组成的组装件的制造入H05K3/00，H05K13/00）
H01L21/77	..在公共衬底中或上面形成的由许多固态元件或集成电路组成的器件的制造或处理（电可编程只读存储器或其多步骤的制造方法入H01L27/115）
H01L21/78	...把衬底连续地分成多个独立的器件（改变表面物理特性或者半导体形状的切割入H01L21/304）
H01L21/82	....制造器件，例如每一个由许多元件组成的集成电路
H01L21/822	.....衬底是采用硅工艺的半导体的（H01L21/8258优先）
H01L21/8232	......场效应工艺
H01L21/8234	.......MIS工艺
H01L21/8238	........互补场效应晶体管，例如CMOS