Invention Grant
US08173536B2 Semiconductor device and method of forming column interconnect structure to reduce wafer stress
有权
半导体器件和形成柱互连结构以减少晶片应力的方法
- Patent Title: Semiconductor device and method of forming column interconnect structure to reduce wafer stress
- Patent Title (中): 半导体器件和形成柱互连结构以减少晶片应力的方法
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Application No.: US12610763Application Date: 2009-11-02
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Publication No.: US08173536B2Publication Date: 2012-05-08
- Inventor: SungWon Cho , TaeWoo Kang
- Applicant: SungWon Cho , TaeWoo Kang
- Applicant Address: SG Singapore
- Assignee: STATS ChipPAC, Ltd.
- Current Assignee: STATS ChipPAC, Ltd.
- Current Assignee Address: SG Singapore
- Agency: Patent Law Group: Atkins & Associates, P.C.
- Agent Robert D. Atkins
- Main IPC: H01L21/44
- IPC: H01L21/44

Abstract:
An interconnect pad is formed over a first substrate. A photoresist layer is formed over the first substrate and interconnect pad. A portion of the photoresist layer is removed to form a channel and expose a perimeter of the interconnect pad while leaving the photoresist layer covering a central area of the interconnect pad. A first conductive material is deposited in the channel of the photoresist layer to form a column of conductive material. The remainder of the photoresist layer is removed. A masking layer is formed around the column of conductive material while exposing the interconnect pad within the column of conductive material. A second conductive material is deposited over the first conductive layer. The second conductive material extends above the column of conductive material. The masking layer is removed. The second conductive material is reflowed to form a column interconnect structure over the semiconductor device.
Public/Granted literature
- US20110101518A1 Semiconductor Device and Method of Forming Column Interconnect Structure to Reduce Wafer Stress Public/Granted day:2011-05-05
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