Invention Grant
US08174011B2 Positional offset measurement pattern unit featuring via-plug and interconnections, and method using such positional offset measurement pattern unit
失效
具有通孔和互连的位置偏移测量图案单元，以及使用这种位置偏移测量图案单元的方法
- Patent Title: Positional offset measurement pattern unit featuring via-plug and interconnections, and method using such positional offset measurement pattern unit
- Patent Title (中): 具有通孔和互连的位置偏移测量图案单元，以及使用这种位置偏移测量图案单元的方法
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Application No.: US12018256Application Date: 2008-01-23
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Publication No.: US08174011B2Publication Date: 2012-05-08
- Inventor: Daisuke Oshida
- Applicant: Daisuke Oshida
- Applicant Address: JP Kanagawa
- Assignee: Renesas Electronics Corporation
- Current Assignee: Renesas Electronics Corporation
- Current Assignee Address: JP Kanagawa
- Agency: Young & Thompson
- Priority: JP2007-057780 20070307
- Main IPC: H01L23/58
- IPC: H01L23/58 ; H01L29/10 ; H01L23/48 ; H01L23/52 ; H01L29/40
Abstract:
In a positional offset measurement pattern unit formed in an insulating layer, a first interconnection is formed in the insulating layer. A via-plug is formed in the insulating layer so as to be electrically connected to the first interconnection. A second interconnection is formed in the insulating layer at substantially the same level as the first interconnection so as to be spaced from the first interconnection by a given distance. A voltage is applied between the first and second interconnections to measure a relative positional offset amount between the via-plug and the second interconnection.
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