Invention Grant
- Patent Title: Integrating three-dimensional high capacitance density structures
- Patent Title (中): 集成三维高电容密度结构
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Application No.: US11505201Application Date: 2006-08-16
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Publication No.: US08174017B2Publication Date: 2012-05-08
- Inventor: Markondeya Raj Pulugurtha , Devarajan Balaraman , Isaac R. Abothu , Rao Tummala , Farrokh Ayazi
- Applicant: Markondeya Raj Pulugurtha , Devarajan Balaraman , Isaac R. Abothu , Rao Tummala , Farrokh Ayazi
- Applicant Address: US GA Atlanta
- Assignee: Georgia Tech Research Corporation
- Current Assignee: Georgia Tech Research Corporation
- Current Assignee Address: US GA Atlanta
- Agency: Troutman Sanders LLP
- Agent Trenton A. Ward, Esq.
- Main IPC: H01L27/108
- IPC: H01L27/108

Abstract:
Disclosed are three-dimensional dielectric structures on high surface area electrodes and fabrication methods. Exemplary structures comprise a copper foil substrate, trench electrodes or high surface area porous electrode structures formed on the substrate, a insulating thin film formed on the surface and laminating the foil on a organic substrate. A variety of materials may be used to make the films including perovksite ceramics such as barium titanate, strontium titanate, barium strontium titanate (BST), lead zirconate titanate (PZT); other intermediate dielectric constant films such as zinc oxide, aluminum nitride, silicon nitride; typical paraelectrics such as tantalum oxide, alumina, and titania. The films may be fabricated using sol-gel, hydrothermal synthesis, anodization or vapor deposition techniques.
Public/Granted literature
- US20070040204A1 Integrating three-dimensional high capacitance density structures Public/Granted day:2007-02-22
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