Invention Grant
US08174070B2 Dual channel trench LDMOS transistors and BCD process with deep trench isolation
有权
双通道沟槽LDMOS晶体管和具有深沟槽隔离的BCD工艺
- Patent Title: Dual channel trench LDMOS transistors and BCD process with deep trench isolation
- Patent Title (中): 双通道沟槽LDMOS晶体管和具有深沟槽隔离的BCD工艺
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Application No.: US12629844Application Date: 2009-12-02
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Publication No.: US08174070B2Publication Date: 2012-05-08
- Inventor: Shekar Mallikarjunaswamy
- Applicant: Shekar Mallikarjunaswamy
- Applicant Address: US CA Sunnyvale
- Assignee: Alpha and Omega Semiconductor Incorporated
- Current Assignee: Alpha and Omega Semiconductor Incorporated
- Current Assignee Address: US CA Sunnyvale
- Agency: Patent Law Group LLP
- Agent Carmen C. Cook
- Main IPC: H01L29/66
- IPC: H01L29/66 ; H01L21/336
Abstract:
A dual channel trench LDMOS transistor includes a substrate of a first conductivity type; a semiconductor layer of a second conductivity type formed on the substrate; a first trench formed in the semiconductor layer where a trench gate is formed in an upper portion of the first trench; a body region of the first conductivity type formed in the semiconductor layer adjacent the first trench; a source region of the second conductivity type formed in the body region and adjacent the first trench; a planar gate overlying the body region; a drain region of the second conductivity type spaced apart from the body region by a drain drift region. The planar gate forms a lateral channel in the body region, and the trench gate in the first trench forms a vertical channel in the body region of the LDMOS transistor.
Public/Granted literature
- US20110127602A1 Dual Channel Trench LDMOS Transistors and BCD Process with Deep Trench Isolation Public/Granted day:2011-06-02
Information query
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