Invention Grant
- Patent Title: Fully depleted silicon-on-insulator CMOS logic
- Patent Title (中): 完全耗尽的绝缘体上硅CMOS逻辑
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Application No.: US13099459Application Date: 2011-05-03
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Publication No.: US08174081B2Publication Date: 2012-05-08
- Inventor: Leonard Forbes
- Applicant: Leonard Forbes
- Applicant Address: US ID Boise
- Assignee: Micron Technology, Inc.
- Current Assignee: Micron Technology, Inc.
- Current Assignee Address: US ID Boise
- Agency: Leffert Jay & Polglaze, P.A.
- Main IPC: H01L31/119
- IPC: H01L31/119
Abstract:
A extractor implanted region is used in a silicon-on-insulator CMOS memory device. The extractor region is reversed biased to remove minority carriers from the body region of partially depleted memory cells. This causes the body region to be fully depleted without the adverse floating body effects.
Public/Granted literature
- US20110204431A1 FULLY DEPLETED SILICON-ON-INSULATOR CMOS LOGIC Public/Granted day:2011-08-25
Information query
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