Invention Grant
- Patent Title: Method for facilitating the stacking of integrated circuits having different areas and an integrated circuit package constructed by the method
- Patent Title (中): 便于堆叠具有不同区域的集成电路的方法以及由该方法构成的集成电路封装
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Application No.: US12730947Application Date: 2010-03-24
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Publication No.: US08174108B2Publication Date: 2012-05-08
- Inventor: Peter Mark O'Neill
- Applicant: Peter Mark O'Neill
- Applicant Address: SG Singapore
- Assignee: Avago Technologies Enterprise IP (Singapore) Pte. Ltd.
- Current Assignee: Avago Technologies Enterprise IP (Singapore) Pte. Ltd.
- Current Assignee Address: SG Singapore
- Main IPC: H01L23/02
- IPC: H01L23/02

Abstract:
An integrated circuit package comprises a package substrate, an application specific integrated circuit (ASIC) having a first area and formed on a first wafer made from a select semiconductor material, a second wafer of the select semiconductor material, and a supplemental-integrated circuit. The supplemental-integrated circuit has a second area different from the first area. The first wafer includes a through-wafer via to couple the ASIC to the package substrate. An active surface of the ASIC is coupled to the second wafer. The second wafer is arranged with a window there through that is sized to closely receive and align one or more bonding interfaces of the supplemental-integrated circuit to respective bonding interfaces of the ASIC. A corresponding method for assembling a die-stacked integrated circuit package is disclosed.
Public/Granted literature
Information query
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