Invention Grant
US08174114B2 Semiconductor package structure with constraint stiffener for cleaning and underfilling efficiency
有权
半导体封装结构,具有约束加强件,用于清洁和底部填充效率
- Patent Title: Semiconductor package structure with constraint stiffener for cleaning and underfilling efficiency
- Patent Title (中): 半导体封装结构,具有约束加强件,用于清洁和底部填充效率
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Application No.: US11300328Application Date: 2005-12-15
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Publication No.: US08174114B2Publication Date: 2012-05-08
- Inventor: Chien-Hsiun Lee , Yk Hsiao
- Applicant: Chien-Hsiun Lee , Yk Hsiao
- Applicant Address: TW Hsin-Chu
- Assignee: Taiwan Semiconductor Manufacturing Go. Ltd.
- Current Assignee: Taiwan Semiconductor Manufacturing Go. Ltd.
- Current Assignee Address: TW Hsin-Chu
- Agency: Birch, Stewart, Kolasch & Birch, LLP
- Main IPC: H01L23/34
- IPC: H01L23/34

Abstract:
A semiconductor package structure with a heat dissipating stiffener and method of fabricating the same are provided. In one embodiment, the package structure comprises a substrate having a front side and a back side; a semiconductor chip mounted on the front surface of the substrate; a thermally-conductive stiffener mounted over the front surface of the substrate and surrounding the chip, the stiffener having a first portion and a second portion, wherein the first portion is wider than the second portion so as to allow for easy egress of a dispenser into a gap between the chip and the substrate; an underfill layer filled and cured in the gap; and a plurality of solder balls mounted on the back surface of the substrate.
Public/Granted literature
- US20070145571A1 Semiconductor package structure with constraint stiffener for cleaning and underfilling efficiency Public/Granted day:2007-06-28
Information query
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