Invention Grant
- Patent Title: Dummy pattern in wafer backside routing
- Patent Title (中): 晶圆背面路由中的虚拟图案
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Application No.: US12756727Application Date: 2010-04-08
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Publication No.: US08174124B2Publication Date: 2012-05-08
- Inventor: Ming-Yen Chiu , Hsien-Wei Chen , Ming-Fa Chen , Shin-Puu Jeng
- Applicant: Ming-Yen Chiu , Hsien-Wei Chen , Ming-Fa Chen , Shin-Puu Jeng
- Applicant Address: TW Hsin-Chu
- Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
- Current Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
- Current Assignee Address: TW Hsin-Chu
- Agency: Slater & Matsil, L.L.P.
- Main IPC: H01L23/48
- IPC: H01L23/48
Abstract:
A device includes a semiconductor substrate including a front side and a backside. A through-substrate via (TSV) penetrates the semiconductor substrate. A dummy metal line is formed on the backside of the semiconductor substrate, and may be connected to the dummy TSV.
Public/Granted literature
- US20110248404A1 Dummy Pattern in Wafer Backside Routing Public/Granted day:2011-10-13
Information query
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