Invention Grant
US08174283B2 Calibration technique for measuring gate resistance of power MOS gate device at wafer level
有权
用于在晶圆级测量功率MOS栅极器件的栅极电阻的校准技术
- Patent Title: Calibration technique for measuring gate resistance of power MOS gate device at wafer level
- Patent Title (中): 用于在晶圆级测量功率MOS栅极器件的栅极电阻的校准技术
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Application No.: US12454004Application Date: 2009-05-11
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Publication No.: US08174283B2Publication Date: 2012-05-08
- Inventor: Anup Bhalla , Sik K. Lui , Daniel Ng
- Applicant: Anup Bhalla , Sik K. Lui , Daniel Ng
- Applicant Address: US CA Sunnyvale
- Assignee: Alpha & Omega Semiconductor, Inc.
- Current Assignee: Alpha & Omega Semiconductor, Inc.
- Current Assignee Address: US CA Sunnyvale
- Agent Bo-In Lin
- Main IPC: G01R31/02
- IPC: G01R31/02 ; H01L21/66
Abstract:
This invention discloses a method for calibrating a gate resistance measurement of a semiconductor power device that includes a step of forming a RC network on a test area on a semiconductor wafer adjacent to a plurality of semiconductor power chips and measuring a resistance and a capacitance of the RC network to prepare for carrying out a wafer-level measurement calibration of the semiconductor power device. The method further includes a step of connecting a probe card to a set of contact pads on the semiconductor wafer for carrying out the wafer-level measurement calibration followed by performing a gate resistance Rg measurement for the semiconductor power chips.
Public/Granted literature
- US20090219044A1 Calibration technique for measuring gate resistance of power MOS gate device at wafer level Public/Granted day:2009-09-03
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