Invention Grant
- Patent Title: Reference voltage circuit
- Patent Title (中): 参考电压电路
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Application No.: US12888799Application Date: 2010-09-23
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Publication No.: US08174309B2Publication Date: 2012-05-08
- Inventor: Hideo Yoshino , Takashi Imura
- Applicant: Hideo Yoshino , Takashi Imura
- Applicant Address: JP Chiba
- Assignee: Seiko Instruments Inc.
- Current Assignee: Seiko Instruments Inc.
- Current Assignee Address: JP Chiba
- Agency: Brinks Hofer Gilson & Lione
- Priority: JP2009-221235 20090925; JP2010-180567 20100811
- Main IPC: G05F1/10
- IPC: G05F1/10

Abstract:
Provided is a reference voltage circuit in which a temperature characteristic of a reference voltage is excellent and a circuit scale is small. In the reference voltage circuit, for example, a temperature correction circuit separated from the reference voltage circuit is not used and a difference voltage between threshold voltages of two E-type NMOS transistors (14 and 15) is added to a threshold voltage of a D-type NMOS transistor to generate a reference voltage (Vref). Therefore, the influence of the D-type NMOS transistor on the reference voltage (Vref), which is a degradation factor of the temperature characteristic of the reference voltage (Vref), may be reduced to suppress a change in tilt and curve of the reference voltage (Vref) with respect to a temperature.
Public/Granted literature
- US20110074496A1 REFERENCE VOLTAGE CIRCUIT Public/Granted day:2011-03-31
Information query
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