A driving circuit includes a receiving module, a data mapping module, a shift register module, a plurality of output channels, and a switching module. The receiving module receives data from a first number of parallel inputs. The data mapping module is coupled to the receiving module for mapping the data from the first number of parallel inputs to a second number of data buses according to a bus mode signal. The shift register module is used for generating a plurality of shift control signals. Each of the output channels latches data on the data buses based on the corresponding shift control signal. The switching module is connected between the shift register module and the output channels for outputting the shift control signals to the plurality of output channels according to the bus mode signal.