A semiconductor storage device includes: a memory cell array that includes a plurality of memory cells having a cell transistor formed on a well subjected to application of a predetermined substrate potential; a memory cell array control circuit that switches the number of memory cells, for use in storage of data of 1 bit in a normal operation state, to m (m is a natural number) and switches the number of memory cells, for use in storage of data of 1 bit in a standby state, to n (n is a natural number larger than m); and a substrate potential control circuit that controls the substrate potential in the normal operation state to a first substrate potential and controls the substrate potential in the standby state to a second substrate potential (the second substrate potential>the first substrate potential).