Invention Grant
- Patent Title: Nonvolatile latch circuit
- Patent Title (中): 非易失性锁存电路
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Application No.: US12746589Application Date: 2008-12-03
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Publication No.: US08174872B2Publication Date: 2012-05-08
- Inventor: Noboru Sakimura , Tadahiko Sugibayashi , Ryusuke Nebashi
- Applicant: Noboru Sakimura , Tadahiko Sugibayashi , Ryusuke Nebashi
- Applicant Address: JP Tokyo
- Assignee: NEC Corporation
- Current Assignee: NEC Corporation
- Current Assignee Address: JP Tokyo
- Priority: JP2007-316397 20071206
- International Application: PCT/JP2008/071940 WO 20081203
- International Announcement: WO2009/072511 WO 20090611
- Main IPC: G11C11/00
- IPC: G11C11/00

Abstract:
A nonvolatile latch circuit includes: first and second inverters cross-coupled to hold 1-bit data; first and second magnetoresistive elements each having first to third terminals; and a current supply circuitry configured to supply a magnetization reversal current for changing the magnetization states of the first and second maqnetoresistive elements in response to the 1-bit data. The power terminal of the first inverter is connected to the first terminal of the first magnetoresistive element and the power terminal of the second inverter is connected to the first terminal of the second magnetoresistive element. The current supply circuitry is configured to supply the magnetization reversal current to the second terminals of the first and second magnetoresistive elements. The third terminal of the first magnetoresistive element is electrically connected to the third terminal of the second magnetoresistive element.
Public/Granted literature
- US20100271866A1 NONVOLATILE LATCH CIRCUIT Public/Granted day:2010-10-28
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