A non-volatile semiconductor memory device includes a NAND cell unit including a plurality of electrically rewritable non-volatile memory cells serially connected. The NAND cell unit has one end connected to a bit line via a first selection gate transistor and the other end connected to a source line via a second selection gate transistor. The non-volatile semiconductor memory device also includes a first dummy cell interposed next to the first selection gate transistor in the NAND cell unit. The non-volatile semiconductor memory device additionally includes a second dummy cell interposed next to the second selection gate transistor in the NAND cell unit. In a data write mode, a first voltage applied to a gate of the first dummy cell is higher than or equal to a second voltage applied to a gate of the second dummy cell.