Invention Grant
US08174904B2 Memory array and method of operating one of a plurality of memory cells
有权
存储器阵列和操作多个存储器单元之一的方法
- Patent Title: Memory array and method of operating one of a plurality of memory cells
- Patent Title (中): 存储器阵列和操作多个存储器单元之一的方法
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Application No.: US12898691Application Date: 2010-10-05
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Publication No.: US08174904B2Publication Date: 2012-05-08
- Inventor: Wen-Yi Hsieh , Ching-Chung Lin , Ken-Hui Chen , Chun-Hsiung Hung
- Applicant: Wen-Yi Hsieh , Ching-Chung Lin , Ken-Hui Chen , Chun-Hsiung Hung
- Applicant Address: TW Hsinchu
- Assignee: MACRONIX International Co., Ltd.
- Current Assignee: MACRONIX International Co., Ltd.
- Current Assignee Address: TW Hsinchu
- Agency: Jianq Chyun IP Office
- Main IPC: G11C11/34
- IPC: G11C11/34 ; G11C16/04
Abstract:
An embodiment of the invention provides a memory array including a plurality of bit lines, a plurality of memory cells and a device. Each of the plurality of memory cells has a first node, a second node and a third node, wherein the third node is coupled to one of the plurality of bit lines. The device couples the plurality of bit lines together to form a common node for one of the plurality of memory cells.
Public/Granted literature
- US20110019473A1 MEMORY ARRAY AND METHOD OF OPERATING ONE OF A PLURALITY OF MEMORY CELLS Public/Granted day:2011-01-27
Information query
