Semiconductor memory device and method of testing the same
Abstract:
A device and a method controlling the device are provided. A first command is supplied to the device in synchronization with a clock signal of a first frequency. The first command is to have the device perform a first operation. The frequency of the clock signal is changed from the first frequency to a second frequency higher than the first frequency. The device performs the first operation in synchronization with the clock signal of the second frequency following changing the frequency of the clock signal.
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