A memory includes a first and a second bit lines (BL); a first and a second sense nodes (SN); a first transfer gate between the 1st-BL and the 1st-SN; a second transfer gate (TG) between the 2nd-BL and the 2nd-SN; a latch circuit latching data to the 1st and 2nd-SN; a first data line (DQ) from the 1st-SN to outside; and a 2nd-DQ from the 2nd-SN to outside, wherein write data is transmitted from the 1st and 2nd-DQ to the 1st and 2nd-SN corresponding to selected cells before the 1st and 2nd-TG are set to be a conductive state, when writing data into the selected cells to be written out of the cells, and write data in the 1st and 2nd-SN corresponding to the selected cells are started to be written into the selected cells, when the 1st and 2nd-TG are set to be a conductive state.