Invention Grant
- Patent Title: High speed digital galvanic isolator with integrated low-voltage differential signal interface
- Patent Title (中): 具有集成低压差分信号接口的高速数字电流隔离器
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Application No.: US12202323Application Date: 2008-09-01
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Publication No.: US08175172B2Publication Date: 2012-05-08
- Inventor: Kenji Yamamoto
- Applicant: Kenji Yamamoto
- Applicant Address: SG Singapore
- Assignee: Avago Technologies ECBU IP (Singapore) Pte. Ltd.
- Current Assignee: Avago Technologies ECBU IP (Singapore) Pte. Ltd.
- Current Assignee Address: SG Singapore
- Main IPC: H04B3/50
- IPC: H04B3/50

Abstract:
Various types of high-speed digital galvanic isolators and corresponding integrated low voltage differential signal (“LVDS”) interfaces are disclosed herein. According to some embodiments, phantom power is provided to one side of a galvanic isolator from the other side of the isolator via a twisted pair cable with shielding interconnecting the two sides, and therefore eliminate the need to provide power to both sides of the galvanic isolator through different power supplies or by way of separate physical wiring being routed and connected to the two opposing sides of the isolator. Such phantom power supply configurations reduce cost, lower power consumption, and increase the number of engineering design options available in a device where high speed serial data communication with low noise are required.
Public/Granted literature
- US20100054345A1 High Speed Digital Galvanic Isolator with Integrated Low-Voltage Differential Signal Interface Public/Granted day:2010-03-04
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