Invention Grant
US08175207B2 ISI pattern-weighted early-late phase detector with jitter correction
有权
具有抖动校正的ISI模式加权早期相位检测器
- Patent Title: ISI pattern-weighted early-late phase detector with jitter correction
- Patent Title (中): 具有抖动校正的ISI模式加权早期相位检测器
-
Application No.: US12539516Application Date: 2009-08-11
-
Publication No.: US08175207B2Publication Date: 2012-05-08
- Inventor: Viet Linh Do , Wei Fu
- Applicant: Viet Linh Do , Wei Fu
- Applicant Address: US CA San Diego
- Assignee: Applied Micro Circuits Corporation
- Current Assignee: Applied Micro Circuits Corporation
- Current Assignee Address: US CA San Diego
- Agency: Law Office of Gerald Maliszewski
- Agent Gerald Maliszewski
- Main IPC: H04L7/00
- IPC: H04L7/00 ; H04L25/00 ; H04L25/40

Abstract:
An inter-symbol interference (ISI) pattern-weighted early-late phase detector is provided. I and Q clocks are generated. The I clock frequency is divided by n, creating a reference clock. A serial data stream is sequentially sampled with the I clock, and with Q clocks having fixed and varied phase delays from the I clock, creating digital I-bit and Q-bit values. The I-bit values and Q-bit values are segmented into n-bit digital words. I clock phase corrections are identified and a modulation factor is determined in response to comparing Q-bit values sampled by the varied delay Q clock. Also identified are bit sequence patterns associated with each I-bit value. Each I-bit value is weighted in response to the identified bit sequence pattern and the identified I clock phase correction. The modulation factor is applied to the weighted average, and I and Q clock phase error signal are generated.
Public/Granted literature
- US20090296867A1 ISI Pattern-Weighted Early-Late Phase Detector with Jitter Correction Public/Granted day:2009-12-03
Information query