Invention Grant
US08176252B1 DMA address translation scheme and cache with modified scatter gather element including SG list and descriptor tables
有权
DMA地址转换方案和具有修改的散列收集元素的缓存，包括SG列表和描述符表
- Patent Title: DMA address translation scheme and cache with modified scatter gather element including SG list and descriptor tables
- Patent Title (中): DMA地址转换方案和具有修改的散列收集元素的缓存，包括SG列表和描述符表
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Application No.: US12203455Application Date: 2008-09-03
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Publication No.: US08176252B1Publication Date: 2012-05-08
- Inventor: Praveen Alexander , Heng Liao
- Applicant: Praveen Alexander , Heng Liao
- Applicant Address: US CA Sunnyvale
- Assignee: PMC-Sierra US, Inc.
- Current Assignee: PMC-Sierra US, Inc.
- Current Assignee Address: US CA Sunnyvale
- Agent Dennis R. Haszko
- Main IPC: G06F13/00
- IPC: G06F13/00
Abstract:
A scatter gather element based caching system is provided along with a modified scatter gather element, that supports efficient logical to physical address translation for arbitrarily aligned and arbitrarily sized fragment (segment) based memory management schemes. This is different from modern CPU implementations with MMUs that support page-based implementations. A primary application of embodiments of the present invention is in DMA applications. The system enables frequent switching of contexts between I/Os using a novel caching technique. An embodiment of the present invention also includes the modification of the conventional scatter-gather element used in DMA for supporting multiple memory spaces, backward list traversals, better error recovery and debugging.
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