One aspect of the embodiments utilizes an information processing apparatus having a plurality of system boards connected via a bus, each system board including a CPU having a cache memory, a main memory that forms a shared memory, and a system controller that manages the CPU and the main memory as well as controls a data transfer of at least one of the cache memory and the main memory by a memory access request, wherein each system controller including a snoop controller that selects a transfer source CPU from transfer source candidate CPUs each having cache memory including a data requested by the memory access request when the data is available in a plurality of cache memories.