The invention describes a method for transferring data between a first clock domain having a first clock rate (CLK1) and at least one additional clock domain having a second clock rate (CLK2), comprising the following for the transfer of data from the first to the second clock domain (CLK1, CLK2): reading in of a data item in accordance with the first clock rate (CLK1) into a first memory (11), and locking of the first memory after saving the data item, signalizing a transfer start after saving the data item in the first memory (11) by means of a transfer start signal (TS), reading out the data item from the first memory, and reading in the data item into a second memory, each according to the second clock signal (CLK2), processing the transfer start signal (TS) according to the second clock signal (CLK2) for generating a transfer end signal (TD), processing the transfer end signal (TD) according to the first clock signal (CLK1) for generating a release signal (TD′) and releasing the first memory as a function of the release signal (TD′).