Invention Grant
- Patent Title: Error detection control system
- Patent Title (中): 错误检测控制系统
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Application No.: US12594311Application Date: 2008-03-13
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Publication No.: US08176387B2Publication Date: 2012-05-08
- Inventor: Shigeo Ohyama
- Applicant: Shigeo Ohyama
- Applicant Address: JP Osaka-shi
- Assignee: Sharp Kabushiki Kaisha
- Current Assignee: Sharp Kabushiki Kaisha
- Current Assignee Address: JP Osaka-shi
- Agency: Morrison & Foerster LLP
- Priority: JP2007-098800 20070404
- International Application: PCT/JP2008/054570 WO 20080313
- International Announcement: WO2008/126609 WO 20081023
- Main IPC: G11C29/00
- IPC: G11C29/00 ; G06F11/00 ; H03M13/00

Abstract:
An error detection control system for a nonvolatile memory comprises: a nonvolatile memory having data areas for a plurality of addresses each including a main data area and a redundant data area for one address; memory control means for controlling on the nonvolatile memory a batch erasing process on a data area group basis, a reading process on the data area basis, a programming process on the data area basis, and an overwriting process on a bit basis; error detecting means for executing the error detecting process based upon the corresponding redundant data; error detecting control means for controlling availability of execution of the error detecting process based upon data types to be classified depending on whether or not the data is subjected to the overwriting process or a storage state indicating whether or not the overwriting process has been executed.
Public/Granted literature
- US20100083050A1 ERROR DETECTION CONTROL SYSTEM Public/Granted day:2010-04-01
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