Exemplary embodiments provide a method for laying out an IC design and the IC design layout. The IC design layout can include one or more gate features placed on an active region including a first pitch (p1) between any two adjacent gate features. Additionally, the IC design layout can include a printable-gate-assist feature placed adjacent to at least one side of the active region, and placed parallel to and at a second pitch (p2) from one first gate feature of the one or more gate features. In various embodiments, a printable-gate-extension feature can be drawn in the design to extend a second gate feature to match a length with a longer neighboring gate feature of the one or more gate features.