Invention Grant
US08176445B1 Method and system for optimizing integrated circuit layout 有权
优化集成电路布局的方法和系统

  • Patent Title: Method and system for optimizing integrated circuit layout
  • Patent Title (中): 优化集成电路布局的方法和系统
  • Application No.: US12181460
    Application Date: 2008-07-29
  • Publication No.: US08176445B1
    Publication Date: 2012-05-08
  • Inventor: Qi-De Qian
  • Applicant: Qi-De Qian
  • Applicant Address: US CA Santa Clara
  • Assignee: Qi-De Qian
  • Current Assignee: Qi-De Qian
  • Current Assignee Address: US CA Santa Clara
  • Main IPC: G06F17/50
  • IPC: G06F17/50
Method and system for optimizing integrated circuit layout
Abstract:
We disclose a method for optimizing integrated circuit layout which comprises analyzing constraint relationship among objects in an initial layout; constructing local modifications to the constraint relationship; forming new constraint relationships by combining initial constraint relationships with their local modifications; and producing a new layout by implementing the new constraint relationships. Local modification to constraints provides a framework for bringing detailed local information into the design process in a highly automated manner, which can be applied to a wide range of situations. We disclose preferred embodiments on improving lithography printability, reducing defect susceptibility, and improving circuit performance such as reducing layout variability and leakage.
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