Invention Grant
- Patent Title: Method and apparatus for circuit partitioning and trace assignment in circuit design
- Patent Title (中): 电路设计中电路分割和跟踪分配的方法和装置
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Application No.: US12942961Application Date: 2010-11-09
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Publication No.: US08176452B2Publication Date: 2012-05-08
- Inventor: Awartika Pandey , Drazen Borkovic , Kenneth S. McElvain
- Applicant: Awartika Pandey , Drazen Borkovic , Kenneth S. McElvain
- Applicant Address: US CA Mountain View
- Assignee: Synopsys, Inc.
- Current Assignee: Synopsys, Inc.
- Current Assignee Address: US CA Mountain View
- Agency: Blakely, Sokoloff, Taylor & Zafman LLP
- Agent Judith A. Szepesi
- Main IPC: G06F17/50
- IPC: G06F17/50

Abstract:
Methods and apparatuses for incremental circuit partitioning and incremental trace assignment. In one embodiment of the present invention, a cost function based on both the partitioning solution and the trace assignment solution is used for the partitioning of a circuit; in reducing the cost function, blocks of circuits are moved among partitions and the trace assignment are updated accordingly to evaluate the cost function. In one embodiment, the traces and nets are grouped according to the partitions they connect for trace assignment. In one embodiment, a flow diagram is constructed for assigning nets to traces; and, maximum flow algorithms are used. In one embodiment, a flow diagram includes feedthrough solutions, in which flow conservation is not preserved at certain nodes. In one embodiment, integer linear programming techniques are used for assigning nets to traces. In one embodiment, a distribution of nets, which defines the numbers of blocks that each net has in each partition, is computed and maintained for efficient determination of the number of nets in net groups.
Public/Granted literature
- US20110055792A1 Method and Apparatus for Circuit Partitioning and Trace Assignment in Circuit Design Public/Granted day:2011-03-03
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