Invention Grant
- Patent Title: Non-invasive timing characterization of integrated circuits using sensitizable signal paths and sparse equations
- Patent Title (中): 使用敏感信号路径和稀疏方程的集成电路的非侵入式定时表征
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Application No.: US12550119Application Date: 2009-08-28
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Publication No.: US08176454B2Publication Date: 2012-05-08
- Inventor: Miodrag Potkonjak
- Applicant: Miodrag Potkonjak
- Applicant Address: US DE Wilmington
- Assignee: Empire Technology Development LLC
- Current Assignee: Empire Technology Development LLC
- Current Assignee Address: US DE Wilmington
- Agency: Schwabe, Williamson & Wyatt, P.C.
- Main IPC: G06F17/50
- IPC: G06F17/50

Abstract:
Techniques for non-invasive, post-silicon characterization of signal propagation delay/timing of devices in an integrated circuit (IC) are generally disclosed. A system of equations may be developed based on a plurality of sensitizable signal paths (SSPs) of the IC for characterizing signal propagation delay or timing of devices within the SSPs. Input Vectors (IVs) may be selected and consecutively applied at one or more input sequential element devices of the IC associated with the SSPs with to produce corresponding output values at one or more output sequential element devices of the IC associated with the SSPs. Various pre-processing and post-processing techniques may be practiced to further improve accuracy of solution of the equations to enable efficient determination of solutions. Example techniques may include variable splitting, device clustering, IV and equation selection, and boosting, among others. Other aspects may also be disclosed and claimed.
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